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@ -5,30 +5,9 @@
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#include <ucontext.h>
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#include <ucontext.h>
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#include <unistd.h>
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#include <unistd.h>
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#define ARCH_NREGS (16 /* GP registers */ + 1 /* for IP */)
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#define ARCH_NREGS 2 // for SP & IP only
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#define ARCH_SIG_JMP_OFF 8
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#define ARCH_SIG_JMP_OFF 8
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/*
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* Register strict ordering>
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* rax = (regs + 0) = 0(%%reg)
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* rbx = (regs + 1) = 8(%%reg)
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* rcx = (regs + 2) = 16(%%reg)
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* rdx = (regs + 3) = 24(%%reg)
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* rbp = (regs + 4) = 32(%%reg)
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* rsp = (regs + 5) = 40(%%reg)
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* rsi = (regs + 6) = 48(%%reg)
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* rdi = (regs + 7) = 56(%%reg)
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* r8 = (regs + 8) = 64(%%reg)
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* r9 = (regs + 9) = 72(%%reg)
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* r10 = (regs + 10) = 80(%%reg)
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* r11 = (regs + 11) = 88(%%reg)
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* r12 = (regs + 12) = 96(%%reg)
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* r13 = (regs + 13) = 104(%%reg)
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* r14 = (regs + 14) = 112(%%reg)
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* r15 = (regs + 15) = 120(%%reg)
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* rip = (regs + 16) = 128(%%reg)
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*/
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typedef uint64_t reg_t;
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typedef uint64_t reg_t;
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/*
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/*
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@ -69,8 +48,8 @@ static void __attribute__((noinline)) arch_context_init(arch_context_t *actx, re
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: "memory", "cc", "rbx");
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: "memory", "cc", "rbx");
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}
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}
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*(actx->regs + 5) = sp;
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*(actx->regs) = sp;
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*(actx->regs + 16) = ip;
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*(actx->regs + 1) = ip;
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}
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}
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static int
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static int
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@ -78,12 +57,12 @@ arch_mcontext_restore(mcontext_t *mc, arch_context_t *ctx)
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{
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{
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assert(ctx != &worker_thread_base_context);
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assert(ctx != &worker_thread_base_context);
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// if ctx->regs[5] is set, this was last in a user-level context switch state!
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// if ctx->regs[0] is set, this was last in a user-level context switch state!
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// else restore mcontext..
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// else restore mcontext..
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if (ctx->regs[5]) {
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if (ctx->regs[0]) {
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mc->gregs[REG_RSP] = ctx->regs[5];
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mc->gregs[REG_RSP] = ctx->regs[0];
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mc->gregs[REG_RIP] = ctx->regs[16] + ARCH_SIG_JMP_OFF;
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mc->gregs[REG_RIP] = ctx->regs[1] + ARCH_SIG_JMP_OFF;
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ctx->regs[5] = 0;
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ctx->regs[0] = 0;
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return 1;
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return 1;
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} else {
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} else {
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@ -99,7 +78,7 @@ arch_mcontext_save(arch_context_t *ctx, mcontext_t *mc)
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{
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{
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assert(ctx != &worker_thread_base_context);
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assert(ctx != &worker_thread_base_context);
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ctx->regs[5] = 0;
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ctx->regs[0] = 0;
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memcpy(&ctx->mctx, mc, sizeof(mcontext_t));
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memcpy(&ctx->mctx, mc, sizeof(mcontext_t));
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}
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}
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@ -127,17 +106,17 @@ arch_context_switch(arch_context_t *ca, arch_context_t *na)
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asm volatile("pushq %%rbp\n\t"
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asm volatile("pushq %%rbp\n\t"
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"movq %%rsp, %%rbp\n\t"
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"movq %%rsp, %%rbp\n\t"
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"movq $2f, 128(%%rax)\n\t"
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"movq $2f, 8(%%rax)\n\t"
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"movq %%rsp, 40(%%rax)\n\t"
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"movq %%rsp, (%%rax)\n\t"
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"cmpq $0, 40(%%rbx)\n\t"
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"cmpq $0, (%%rbx)\n\t"
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"je 1f\n\t"
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"je 1f\n\t"
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"movq 40(%%rbx), %%rsp\n\t"
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"movq (%%rbx), %%rsp\n\t"
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"jmpq *128(%%rbx)\n\t"
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"jmpq *8(%%rbx)\n\t"
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"1:\n\t"
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"1:\n\t"
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"call worker_thread_sandbox_switch_preempt\n\t"
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"call worker_thread_sandbox_switch_preempt\n\t"
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".align 8\n\t"
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".align 8\n\t"
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"2:\n\t"
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"2:\n\t"
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"movq $0, 40(%%rbx)\n\t"
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"movq $0, (%%rbx)\n\t"
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".align 8\n\t"
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".align 8\n\t"
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"3:\n\t"
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"3:\n\t"
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"popq %%rbp\n\t"
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"popq %%rbp\n\t"
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