ck_pr/x86_64: cleanup documentation around semantics.

A note has also been added around some ambiguity with respect to WC
memory and relaxed memory semantics (so, heavier-weight mfence semantics
for strict acquire-release interface).

All fences related to atomic operations have been removed as they were
just unnecessary, and so, confusing.
cos
Samy Al Bahra 7 years ago
parent a8b9f7f411
commit 4042fea5a8

@ -58,8 +58,8 @@
#endif #endif
/* /*
* Prevent speculative execution in busy-wait loops (P4 <=) * Prevent speculative execution in busy-wait loops (P4 <=) or "predefined
* or "predefined delay". * delay".
*/ */
CK_CC_INLINE static void CK_CC_INLINE static void
ck_pr_stall(void) ck_pr_stall(void)
@ -75,18 +75,39 @@ ck_pr_stall(void)
__asm__ __volatile__(I ::: "memory"); \ __asm__ __volatile__(I ::: "memory"); \
} }
CK_PR_FENCE(atomic, "sfence") /* Atomic operations are always serializing. */
CK_PR_FENCE(atomic_store, "sfence") CK_PR_FENCE(atomic, "")
CK_PR_FENCE(atomic_load, "mfence") CK_PR_FENCE(atomic_store, "")
CK_PR_FENCE(store_atomic, "sfence") CK_PR_FENCE(atomic_load, "")
CK_PR_FENCE(load_atomic, "mfence") CK_PR_FENCE(store_atomic, "")
CK_PR_FENCE(load_atomic, "")
/* Traditional fence interface. */
CK_PR_FENCE(load, "lfence") CK_PR_FENCE(load, "lfence")
CK_PR_FENCE(load_store, "mfence") CK_PR_FENCE(load_store, "mfence")
CK_PR_FENCE(store, "sfence") CK_PR_FENCE(store, "sfence")
CK_PR_FENCE(store_load, "mfence") CK_PR_FENCE(store_load, "mfence")
CK_PR_FENCE(memory, "mfence") CK_PR_FENCE(memory, "mfence")
/* Below are stdatomic-style fences. */
/*
* Provides load-store and store-store ordering. However, Intel specifies that
* the WC memory model is relaxed. It is likely an sfence *is* sufficient (in
* particular, stores are not re-ordered with respect to prior loads and it is
* really just the stores that are subject to re-ordering). However, we take
* the conservative route as the manuals are too ambiguous for my taste.
*/
CK_PR_FENCE(release, "mfence") CK_PR_FENCE(release, "mfence")
/*
* Provides load-load and load-store ordering. The lfence instruction ensures
* all prior load operations are complete before any subsequent instructions
* actually begin execution. However, the manual also ends up going to describe
* WC memory as a relaxed model.
*/
CK_PR_FENCE(acquire, "mfence") CK_PR_FENCE(acquire, "mfence")
CK_PR_FENCE(acqrel, "mfence") CK_PR_FENCE(acqrel, "mfence")
CK_PR_FENCE(lock, "mfence") CK_PR_FENCE(lock, "mfence")
CK_PR_FENCE(unlock, "mfence") CK_PR_FENCE(unlock, "mfence")

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