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@ -52,42 +52,6 @@
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#define CK_PR_LOCK_PREFIX "lock "
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#define CK_PR_LOCK_PREFIX "lock "
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#endif
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#endif
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/*
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* Prevent speculative execution in busy-wait loops (P4 <=)
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* or "predefined delay".
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*/
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CK_CC_INLINE static void
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ck_pr_stall(void)
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{
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__asm__ __volatile__("pause" ::: "memory");
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return;
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}
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/*
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* IA32 has strong memory ordering guarantees, so memory
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* fences are enabled if and only if the user specifies that
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* that the program will be using non-temporal instructions.
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* Otherwise, an optimization barrier is used in order to prevent
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* compiler re-ordering of loads and stores across the barrier.
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*/
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#define CK_PR_FENCE(T, I) \
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CK_CC_INLINE static void \
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ck_pr_fence_strict_##T(void) \
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{ \
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__asm__ __volatile__(I ::: "memory"); \
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} \
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CK_CC_INLINE static void ck_pr_fence_##T(void) \
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{ \
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__asm__ __volatile__("" ::: "memory"); \
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}
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CK_PR_FENCE(load, "lfence")
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CK_PR_FENCE(load_depends, "")
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CK_PR_FENCE(store, "sfence")
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CK_PR_FENCE(memory, "mfence")
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#undef CK_PR_FENCE
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/*
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/*
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* Atomic fetch-and-store operations.
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* Atomic fetch-and-store operations.
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*/
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*/
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@ -553,12 +517,9 @@ ck_pr_cas_##S##_##W##_value(T *t, T c[W], T s[W], T *v) \
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CK_PR_CAS_V(char, 8, char)
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CK_PR_CAS_V(char, 8, char)
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CK_PR_CAS_V(int, 2, int)
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CK_PR_CAS_V(int, 2, int)
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CK_PR_CAS_V(uint, 2, unsigned int)
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CK_PR_CAS_V(uint, 2, unsigned int)
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CK_PR_CAS_V(64, 1, uint64_t)
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CK_PR_CAS_V(16, 4, uint16_t)
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CK_PR_CAS_V(16, 4, uint16_t)
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CK_PR_CAS_V(8, 8, uint8_t)
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CK_PR_CAS_V(8, 8, uint8_t)
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#define ck_pr_cas_64_value(A, B, C, D) ck_pr_cas_64_1_value((A), &(B), &(C), (D))
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#undef CK_PR_CAS_V
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#undef CK_PR_CAS_V
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/*
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/*
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