diff --git a/include/gcc/ppc/ck_pr.h b/include/gcc/ppc/ck_pr.h
index c82e217..7a7d0df 100644
--- a/include/gcc/ppc/ck_pr.h
+++ b/include/gcc/ppc/ck_pr.h
@@ -67,6 +67,8 @@ ck_pr_stall(void)
 		__asm__ __volatile__(I ::: "memory");   \
 	}
 
+CK_PR_FENCE(atomic, "lwsync")
+CK_PR_FENCE(atomic_atomic, "lwsync")
 CK_PR_FENCE(atomic_store, "lwsync")
 CK_PR_FENCE(atomic_load, "sync")
 CK_PR_FENCE(store_atomic, "lwsync")
diff --git a/include/gcc/ppc64/ck_pr.h b/include/gcc/ppc64/ck_pr.h
index 457efda..2aa145d 100644
--- a/include/gcc/ppc64/ck_pr.h
+++ b/include/gcc/ppc64/ck_pr.h
@@ -70,6 +70,8 @@ ck_pr_stall(void)
  * These are derived from:
  *     http://www.ibm.com/developerworks/systems/articles/powerpc.html
  */
+CK_PR_FENCE(atomic, "lwsync")
+CK_PR_FENCE(atomic_atomic, "lwsync")
 CK_PR_FENCE(atomic_store, "lwsync")
 CK_PR_FENCE(atomic_load, "sync")
 CK_PR_FENCE(store_atomic, "lwsync")
diff --git a/include/gcc/sparcv9/ck_pr.h b/include/gcc/sparcv9/ck_pr.h
index 29b9f9c..076e378 100644
--- a/include/gcc/sparcv9/ck_pr.h
+++ b/include/gcc/sparcv9/ck_pr.h
@@ -67,6 +67,8 @@ ck_pr_stall(void)
  * Atomic operations are treated as both load and store
  * operations on SPARCv9.
  */
+CK_PR_FENCE(atomic_atomic, "membar #StoreStore")
+CK_PR_FENCE(atomic, "membar #StoreStore")
 CK_PR_FENCE(atomic_store, "membar #StoreStore")
 CK_PR_FENCE(atomic_load, "membar #StoreLoad")
 CK_PR_FENCE(store_atomic, "membar #StoreStore")
diff --git a/include/gcc/x86/ck_pr.h b/include/gcc/x86/ck_pr.h
index eed49ba..bbed9bf 100644
--- a/include/gcc/x86/ck_pr.h
+++ b/include/gcc/x86/ck_pr.h
@@ -70,6 +70,8 @@ ck_pr_stall(void)
 		__asm__ __volatile__(I ::: "memory");	\
 	}
 
+CK_PR_FENCE(atomic, "sfence")
+CK_PR_FENCE(atomic_atomic, "sfence")
 CK_PR_FENCE(atomic_store, "sfence")
 CK_PR_FENCE(atomic_load, "mfence")
 CK_PR_FENCE(store_atomic, "sfence")